Field of the Invention
This invention relates generally to vertical capacitors on integrated circuits (ICs), and more particularly to a vertical capacitor contact arrangement and method of fabricating same.
Description of the Related Art
A conventional imaging array comprises an array of pixels, each of which includes a photodetector and the input circuit of a “readout IC” (ROIC) which contains both a capacitor which stores the charge generated by the photodetector in response to light, and electrical circuitry to convey the charge from the photodiode to the capacitor and from the capacitor to further processing circuitry of the ROIC. The ROIC and charge storage capacitors are typically fabricated together using an electronic circuit process, such as CMOS, with the size of each charge storage capacitor limited in part by the size of each pixel and the complexity of the circuit.
Problems may arise when a high-density imaging array is needed. A higher density array requires that the pixel size be small. However, a significant limitation is encountered when attempting to scale to smaller pixel size, in that a smaller pixel necessitates a smaller charge storage capacitor, which serves to reduce the amount of charge that can be stored. This has an adverse effect on the array's sensitivity, typically reflected in the “noise equivalent differential temperature” (NEDT) value, which is a measure of the lowest signal flux level that can be detected by the array. The NEDT value might be lowered by making the charge storage capacitors larger, but this would consume circuit area that might otherwise be used to increase circuit functionality. These factors combine to impede the realization of high performance (low NEDT), high-functionality imaging arrays with small pixel pitch.
One way of overcoming the limitations associated with the ROIC and charge storage capacitors being fabricated together is to provide a separate charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer may be, for example, vertical capacitors comprising a microstructured surface coated with sequential conductive-insulating-conductive thin-film coatings. However, problems can arise with some vertical capacitor designs. Electrical contact needs to be made to the top and bottom conductive layers of each capacitor. In some cases, the recesses in which metal is deposited to make contact to the top conductive layer can be overetched. The corners of the tops of the walls between the trenches are particularly vulnerable to overetching. This can result in damage to or breaching of the dielectric layer which results in reduced breakdown voltage or shorting. In addition, the trenches are often not completely filled with the planarizing oxide layer, but merely pinched off. Overetching can breach the pinchoff area, opening the voids in the trenches to copper plating which results in plating non-uniformity and extra stress during subsequent thermal cycling events.
The overetching problem is exacerbated at the edges of a capacitor array where there is a sharp step from the plateau of the array down to the rest of the field. The chemical-mechanical planarization process acts to smooth out this transition, resulting in an extra thin layer of planarization oxide at the edges of the field.